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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Quad 3-State Bus Transceiver
High-Performance Silicon-Gate CMOS
The MC74HC242 is identical in pinout to the LS242. The device inputs are compatible with Standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. This quad bus transceiver is designed for asynchronous two-way communications between data buses. The states of the Output Enables (A-to-B Enable and B-to-A Enable) determine both the direction of data flow (from A to B or from B to A) and the modes of the Data Ports (input, output, or high-impedance).
14
MC74HC242
N SUFFIX PLASTIC PACKAGE CASE 646-06
1
ORDERING INFORMATION MC74HCXXXN Plastic
* * * * * * *
Output Drive Capability: 15 LSTTL Loads Outputs Directly Interface to CMOS, NMOS and TTL Operating Voltage Range: 2 to 6V Low Input Current: 1A High Noise Immunity Characteristic of CMOS Devices In Compliance With the JEDEC Standard No. 7A Requirements Chip Complexity: 130 FETs or 32.5 Equivalent Gates LOGIC DIAGRAM
Control Inputs A-to-B Enable H L H L B-to-A Enable H H L L Data Port Status A O Z Z I B I Z Z O
FUNCTION TABLE
A1 A2 A3 A4
3 4 5 6
11 10 9 8
I = Input; O = Output, O = Inverting Output Z = High Impedance B1 B2 B3 B4
A Data Port
B Data Port
Output EnableS
A-TO-B ENABLE B-TO-A ENABLE
1 13
Pin 14 = VCC Pin 7 = GND Pins 2, 12 = No Connection
Pinout: 14-Lead Plastic Package (Top View)
B-to-A VCC Enable NC 14 13 12 B1 11 B2 10 B3 9 B4 8
1
2
3 A1
4 A2
5 A3
6 A4
7 GND
A-to-B NC Enable
NC = No Connection
10/95
(c) Motorola, Inc. 1995
1
REV 6
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MC74HC242
MAXIMUM RATINGS*
Symbol VCC Vin Parameter Value Unit V V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 1.5 to VCC + 1.5 - 0.5 to VCC + 0.5 20 35 75 750 VI/O Iin DC Output Voltage (Referenced to GND) DC Input Current, per Pin mA mA mA II/O DC Output Current, per Pin ICC PD DC Supply Current, VCC and GND Pins Power Dissipation in Still Air Storage Temperature Plastic DIP mW Tstg TL - 65 to + 150 260
_C _C
Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP Package
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
v
v
* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol VCC Parameter
Min 2.0 0
Max 6.0
Unit V V
DC Supply Voltage (Referenced to GND)
Vin, Vout TA
DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature Range, All Package Types Input Rise/Fall Time (Figure 1)
VCC
- 55 0 0 0
+ 125 1000 500 400
_C
ns
tr, tf
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
DC CHARACTERISTICS (Voltages Referenced to GND)
Symbol VIH
Parameter Minimum High-Level Input Voltage
Condition Vout = 0.1V or VCC -0.1V |Iout| 20A Vout = 0.1V or VCC - 0.1V |Iout| 20A Vin = VIH or VIL |Iout| 20A Vin =VIH or VIL |Iout| 6.0mA |Iout| 7.8mA
VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0
Guaranteed Limit -55 to 25C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.98 5.48 0.1 0.1 0.1 0.26 0.26 0.1 0.5 85C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.84 5.34 0.1 0.1 0.1 0.33 0.33 1.0 5.0 125C 1.50 3.15 4.20 0.3 0.9 1.2 1.9 4.4 5.9 3.70 5.20 0.1 0.1 0.1 0.40 0.40 1.0 10.0 A A V Unit V
VIL
Maximum Low-Level Input Voltage
V
VOH
Minimum High-Level Output Voltage
V
VOL
Maximum Low-Level Output Voltage
Vin = VIH or VIL |Iout| 20A Vin = VIH or VIL |Iout| 6.0mA |Iout| 7.8mA
4.5 6.0 6.0 6.0
Iin IOZ
Maximum Input Leakage Current Maximum Three-State Leakage Current Maximum Quiescent Supply Current (per Package)
Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND
Vin = VCC or GND 6.0 8 80 160 A Iout = 0A NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). ICC
MOTOROLA
2
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC242
AC CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
Symbol tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL Cin Cout Parameter Maximum Propagation Delay, A to B or B to A (Figures 2 and 4) Maximum Propagation Delay, Output Enable to Output A or B (Figures 3 and 5) Maximum Propagation Delay, Output Enable to Output A or B (Figures 3 and 5) Maximum Output Transition Time, Any Output (Figures 2 and 4) Maximum Input Capacitance Maximum Three-State Output Capacitance (Output in High Impedance State) VCC V 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Guaranteed Limit -55 to 25C 100 20 17 150 30 26 150 30 26 60 12 10 10 15 85C 125 25 21 190 38 33 190 38 33 75 15 13 10 15 125C 150 30 26 225 45 38 225 45 38 90 18 15 10 15 Unit ns
ns
ns
ns
pF pF
NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Dissipation Capacitance (Per Transceiver)* 31 pF * Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
PIN DESCRIPTIONS
DATA PORTS A1-A4 (Pins 3,4,5,6) and B1-B4 (Pins 11,10,9,8) Data on these pins may be transferred between data buses. Depending upon the states of the Output Enables, these pins may be inputs, outputs or open circuits (high-impedance). CONTROL INPUTS A-to-B Enable (Pin 1) and B-to-A Enable (Pin 13) Data on these Output Enables determine both the direction of the data flow (from A to B or from B to A) and the states of the outputs (standard or high impedance), according to the Function Table.
High-Speed CMOS Logic Data DL129 -- Rev 6
3
MOTOROLA
MC74HC242
VCC
One of Four Transceivers A (I/O)
VCC
B (I/O)
A-to-B 1 Enable
B-to-A 13 Enable
Figure 1. Expanded Logic Diagram
SWITCHING WAVEFORMS
tr 90% Input A or B tPHL 90% Output A or B tTHL 50% 10% Output A or B tTLH 50% High Impedance tPZH tPHZ 90% VOH 50% 10% tPLH GND Output A or B 50% 10% VOL tf VCC Output Enable VCC 50% tPZL tPLZ 50% GND High Impedance
Figure 2.
Figure 3.
TEST CIRCUITS
TEST POINT OUTPUT DEVICE UNDER TEST CL* DEVICE UNDER TEST OUTPUT TEST POINT 1k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ and tPZH.
CL*
*Includes all probe and jig capacitance
*Includes all probe and jig capacitance
Figure 4.
Figure 5.
MOTOROLA
4
High-Speed CMOS Logic Data DL129 -- Rev 6
MC74HC242
OUTLINE DIMENSIONS
N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L
14 8 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
B
1 7
A F C N H G D
SEATING PLANE
L
J K M
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High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
5
*MC74HC242/D*
MC74HC242/D MOTOROLA

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